The present invention relates to an erasable and programmable non-volatile memory device. More particularly, the invention relates to a high voltage generator circuit adapted for incorporation into a flash memory device.
Semiconductor memory devices may be roughly divided into volatile and non-volatile type devices. Volatile memory devices are characterized by an inability to retain stored data in the absence of applied electrical power. In contrast, non-volatile memory devices are able to retain stored data even in the absence of applied power. Conventional non-volatile memory devices include mask ROMs, programmable ROMs, erasable and programmable ROMs, electrically erasable and programmable ROMs, and the like. Among commercially available non-volatile memory devices, flash memory devices afford several notable advantages, including an ability to block erase memory cells, etc. As a result, flash memory is widely used to applications such as computers and memory cards needing high-speed operations.
Conventional flash memory devices may be divided into NOR type flash memory and NAND type flash memory based on the particular interconnection between memory cells and associated bit lines. For example, the NOR flash memory device is configured such that two or more cell transistors are connected in parallel to one bit line.
NOR flash memory may be programmed using an electrical phenomenon known as channel hot electron injection and may be erased using another electrical phenomenon known as Fowler-Nordheim (F-N) tunneling. NOR flash memory suffers from disadvantages associated with high density integration due to large current consumption, but also offers advantages related to high-speed memory operations.
NAND flash memory is configured such that two or more cell transistors are connected in series to one bit line. NAND flash memory may be both programmed and erased using F-N tunneling. NAND flash memory offers greater ease of device integration because it consumes relatively less current than NOR flash memory.
Flash memory functions in accordance with basic operations referred to as program, erase and read. Each of these basic operations requires the timely application of certain voltages to signal lines (e.g., word lines, bit lines, etc.) connected memory cells in an array. Flash memory operations require that some of these voltages be higher than the level of commonly applied power supply voltages. (Hereafter, any voltage applied to a flash memory array having a level higher than a power supply voltage applied flash memory will be term “a high voltage”).
FIGS. 1 and 2 are, respectively, circuit diagram and corresponding waveform diagram showing one example of a conventional high voltage generator circuit. More detail regarding this exemplary high voltage generator circuit may be obtained by reviewing U.S. Pat. No. 5,642,309 entitled “Auto-Program Circuit in a Nonvolatile Semiconductor Memory Device,” the subject matter of which is hereby incorporated by reference.
Referring to FIG. 1, as an output voltage of a high voltage generator circuit 50, a program voltage VPGM is divided by a trimming circuit 30 known as a voltage divider circuit. A divided voltage is compared with a reference voltage VREF by a comparator 40 A high voltage generation control circuit 20 controls supply of a clock signal to a high voltage generator 10 according to the comparison result. The high voltage generator 10 is known as a charge pump and generates the program voltage VPGM in response to clock signals ØPP and /ØPP. The high voltage generator circuit 50 controls an ON/OFF period for the high voltage generator 10 according to a comparison result between the divided voltage and the reference voltage VREF.
In the foregoing high voltage generation scheme, a delay period for turning OFF the charge pump once the program voltage VPGM has reached its target level (V_TARGET) is defined. Such a delay period is inevitable in a high voltage generation scheme having a feedback loop path including an RC delay. During the delay period, clock signals ØPP and /ØPP continue to be generated and applied to the high voltage generator 10. Application of these clock signals during the delay period causes the program voltage VPGM to attempt to increase above its target level (V_TARGET). However, feedback limiting drives the program voltage VPGM back down following increase above the target level (V_TARGET). This effect is illustrated in FIG. 2. The resulting program voltage now includes an upper level ripple.